In computer systems, data is frequently transferred between devices connected to different busses. For example, a disk drive connected to a standard I/O bus may be requested to transfer data to a main memory connected to a system bus. Data transfers between two such busses normally occur through an interface buffer connected between the busses. The data buffer is used to temporarily store the data as it is transferred between the devices. The need to buffer data arises because the receiver may be busy when the data is transferred, or because the transfer rates and/or bus widths of the transmitter and receiver are different.
A conventional interface is a first-in first-out (FIFO) buffer in which data elements (typically data bytes) are read out in the same order in which they are read into the buffer. A dual-ported FIFO allows data to be simultaneously read from and written to the buffer. Thus, data may be transferred from a disk drive to the buffer at the operating frequency of the disk drive, and, after a predetermined amount of data is stored, the data may be transferred or burst from the buffer to main memory at the relatively faster operating frequency of main memory. Control of the buffer, or at least monitoring of the amount of data transferred, is normally provided by the system processor.
A buffer may be combined with control logic to form an interface device between the two busses for transferring data through the buffer. For example, such an interface device may receive a request from a processor to transfer a designated number of data bytes from a disk drive to the system's main memory. The interface device may then take control of the transfer, providing a signal to the processor when the transfer is complete. In order to determine when to generate the transfer complete signal, the number of bytes actually transferred must be accurately tracked. In addition, both the transmitting and receiving devices must be notified when the transfer is complete.
The number of logic gates required to implement an interface device capable of tracking large block transfers can consume excessive chip space. This can have an adverse impact on chip costs.